Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Decimal Floating-Point: Algorism for Computers
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
A High-Frequency Decimal Multiplier
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Decimal Multiplication with Efficient Partial Product Generation
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
A New Family of High.Performance Parallel Decimal Multipliers
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
IEEE Transactions on Computers
Fully Redundant Decimal Arithmetic
ARITH '09 Proceedings of the 2009 19th IEEE Symposium on Computer Arithmetic
Improving the Speed of Parallel Decimal Multiplication
IEEE Transactions on Computers
Computer Arithmetic: Algorithms and Hardware Designs
Computer Arithmetic: Algorithms and Hardware Designs
Decimal floating-point support on the IBM system z10 processor
IBM Journal of Research and Development
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Hardware support for decimal arithmetic has become an important focal point, both in the research arena and in commercial processor developments. Like their binary counterparts, decimal multipliers can be designed in a variety of ways, offering area and speed trade-offs. Pipelined array multipliers support high throughput, making them attractive in multiply-intensive applications. We propose two different architectures for decimal array multipliers based on (1) precomputed multiples and (2) decimal digit-multipliers. We compare the VLSI area and delay parameters of the resulting array multiplier designs with each other and with those of binary array multipliers covering the same range of inputs.