Design and evaluation of decimal array multipliers
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Design and microarchitecture of the IBM system z10 microprocessor
IBM Journal of Research and Development
A survey of hardware designs for decimal arithmetic
IBM Journal of Research and Development
Error-free algorithm and architecture of radix-10 logarithmic converter
Computers and Electrical Engineering
Mining for paths in flow graphs
ICDM'10 Proceedings of the 10th industrial conference on Advances in data mining: applications and theoretical aspects
Mining opportunities for code improvement in a just-in-time compiler
CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
A study of decimal left shifters for binary numbers
Information and Computation
Application-driven energy-efficient architecture explorations for big data
Proceedings of the 1st Workshop on Architectures and Systems for Big Data
Performance innovation in the IBM zEnterprise 196 processor
IBM Journal of Research and Development
Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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The IBM System z10 includes four microprocessor cores—each with a private 3-Mbyte cache—and integrated accelerators for decimal floating-point computation, cryptography, and data compression. A separate SMP hub chip provides a shared third-level cache and interconnect fabric for multiprocessor scaling. This article focuses on the high-frequency design techniques used to achieve a 4.4-GHz system, and on the pipeline design that optimizes z10's CPU performance.