Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Introduction to Algorithms
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Proceedings of the 43rd annual Design Automation Conference
Sub-threshold design: the challenges of minimizing circuit energy
Proceedings of the 2006 international symposium on Low power electronics and design
Optimizing finfet technology for high-speed and low-power design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
FinFET Based SRAM Design for Low Standby Power Applications
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
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FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel control, reduced random dopant fluctuation, high ON/OFF current ratio, lower energy consumption, etc. Key characteristics of FinFET operating in the sub/near-threshold region are very different from those in the strong-inversion region. This paper first introduces an analytical transregional FinFET model with high accuracy in both sub- and near-threshold regimes. Next, the paper extends the well-known and widely-adopted logical effort delay calculation and optimization method to FinFET circuits operating in multiple voltage (sub/near/super-threshold) regimes. More specifically, a joint optimization of gate sizing and adaptive independent gate control is presented and solved in order to minimize the delay of FinFET circuits operating in multiple voltage regimes. Experimental results on a 32nm Predictive Technology Model for FinFET demonstrate the effectiveness of the proposed logical effort-based delay optimization framework.