Sub-threshold design: the challenges of minimizing circuit energy

Authors:
B. H. Calhoun;A. Wang;N. Verma;A. Chandrakasan
Affiliations:
University of Virginia;Texas Instruments;Massachussetts Institute of Technology;Massachussetts Institute of Technology
Venue:
Proceedings of the 2006 international symposium on Low power electronics and design
Year:
2006

Citing 0
Cited 2

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VLSI Design
Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method

Proceedings of the International Conference on Computer-Aided Design

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Abstract

In this paper, we identify the key challenges that oppose sub-threshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges.