Real-Time 2-D Feature Detection on a Reconfigurable Computer
CVPR '98 Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition
Pipelining of double precision floating point division and square root operations
Proceedings of the 44th annual Southeast regional conference
A system for real-time 2-D feature detection based on field programmable gate arrays
Integrated Computer-Aided Engineering
OpenFPGA CoreLib core library interoperability effort
Parallel Computing
Parameterizable floating-point library for arithmetic operations in FPGAs
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Signal Processing Systems
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The square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtracter. The operation latency is 25 clock cycles and the issue rate is 24 clock cycles. The other is high-throughput pipelined implementation that uses multiple adder/subtracters. The operation latency is 15 clock cycles and the issue rate is one clock cycle. It means that the pipelined implementation is capable of accepting a square root instruction on every clock cycle.