MIPS RISC architectures
Placement-Oriented Modeling of Partially Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Extensible On-Chip Peripherals
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Zero logic overhead integration of partially reconfigurable modules
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Automatic floorplanning and interface synthesis of island style reconfigurable systems with GOAHEAD
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Dynamic Partial Reconfiguration of FPGAs partitions the configurable logic fabric into static and reconfigurable regions. The reconfigurable regions' functionality changes at run time while the static regions continue unperturbed. The reconfigurable and static regions interface via fixed connection points ("bus macros"). We introduce the notion of a fitness score as the measure of how well the combined designs meet their timing constraints, subject to a given bus macro placement. We present a tool that uses design-space exploration to obtain automatic, near-optimal placements. The tool achieves 76% better fitness scores over manual placements. The location of the bus macros around a region has a noticeable impact on the timings, and we found that this is accurately reflected on our fitness score. We also found that following the accepted best design practices leads to quantifiably sub-optimal placements, underscoring the need for such a tool.