MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Computer
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
Run-time system for an extensible embedded processor with dynamic instruction set
Proceedings of the conference on Design, automation and test in Europe
Fine- and Coarse-Grain Reconfigurable Computing
Fine- and Coarse-Grain Reconfigurable Computing
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Introduction to Reconfigurable Computing: Architectures, Algorithms, and Applications
Architectural exploration of the ADRES coarse-grained reconfigurable array
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
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Processors that deploy fine-grained reconfigurable fabrics to implement application-specific accelerators on-demand obtained significant attention within the last decade. They trade-off the flexibility of general-purpose processors with the performance of application-specific circuits without tailoring the processor towards a specific application domain like Application Specific Instruction Set Processors (ASIPs). Vast amounts of reconfigurable processors have been proposed, differing in multifarious architectural decisions. However, it has always been an open question, which of the proposed concepts is more efficient in certain application and/or parameter scenarios. Various reconfigurable processors were investigated in certain scenarios, but never before a systematic design space exploration across diverse reconfigurable processor concepts has been conducted with the aim to aid a designer of a reconfigurable processor. We have developed a first-of-its-kind comprehensive design space exploration tool that allows to systematically explore diverse reconfigurable processors and architectural parameters. Our tool allows presenting the first cross-architectural design space exploration of multiple fine-grained reconfigurable processors on a fair comparable basis. After categorizing fine-grained reconfigurable processors and their relevant parameters, we present our tool and an in-depth analysis of reconfigurable processors within different relevant scenarios.