Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A quantitative study and estimation models for extensible instructions in embedded processors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Battery-aware instruction generation for embedded processors
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Chip size estimation for SOC design space exploration
Journal of Systems Architecture: the EUROMICRO Journal
RISPP: rotating instruction set processing platform
Proceedings of the 44th annual Design Automation Conference
Run-time instruction set selection in a transmutable embedded processor
Proceedings of the 45th annual Design Automation Conference
Run-time system for an extensible embedded processor with dynamic instruction set
Proceedings of the conference on Design, automation and test in Europe
Trend and Challenge on System-on-a-Chip Designs
Journal of Signal Processing Systems
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Journal of Systems Architecture: the EUROMICRO Journal
Computers and Electrical Engineering
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Journal of Signal Processing Systems
ACM SIGDA Newsletter
Cross-architectural design space exploration tool for reconfigurable processors
Proceedings of the Conference on Design, Automation and Test in Europe
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applying autonomic principles for workload management in multi-core systems on chip
Proceedings of the 8th ACM international conference on Autonomic computing
Design entropy concept: a measurement for complexity
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Morphable structures for reconfigurable instruction set processors
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Autonomic workload management for multi-core processor systems
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
Hi-index | 4.10 |
Current mainstream system-on-chip (SoC) designs do not yet fully exploit the 100 million transistors per chip possible with today's mainstream silicon technology. System-level design and extensible processors can bridge the gap between silicon technology and actual SoC complexities. However, SoCs comprising 1,000 processors at a billion transistors by the end of the decade will require research advances in key areas like ESL design methodologies and NoC architectures.