Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
IEEE Transactions on Computers
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
The Development of an Operating System for Reconfigurable Computing
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
IEEE Transactions on Computers
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
Journal of VLSI Signal Processing Systems
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
IEEE Transactions on Computers
ReconOS: Multithreaded programming for reconfigurable computers
ACM Transactions on Embedded Computing Systems (TECS)
A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
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To support dynamic applications, FPGAs will need to have a software operating system equivalent resource manager. An abstract FPGA architecture is the foundation to develop such an FPGA resource manager. Previous research projects work on the FPGA abstraction by abstracting the computing and/or the communication resources. However, various constraints made their proposals practically less useful due to the performance and/or the area overheads. We develop a low overhead abstract FPGA architecture that has the important features such as dynamically sized reconfigurable regions, deterministic communications among regions, clock network management and in-circuit debugging for regions. The architecture is demonstrated by implementing three applications on the Xilinx Virtex 5 FPGAs. We evaluate our work by comparing the area and performance overheads due to the abstractions between the abstracted and the non-abstracted applications. Experimental results show that additional resources required due to abstractions are found to be 6.4% on average. This is achieved with low overheads on the timing performance.