Research on the online evaluation approach for the digital evolvable hardware

Authors:
Rui Yao;You-ren Wang;Sheng-lin Yu;Gui-jun Gao
Affiliations:
College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu, China;College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu, China;College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu, China;College of Automation and Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, Jiangsu, China
Venue:
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Year:
2007

Citing 8
Cited 1

Genetic Algorithms and the Immune System

PPSN I Proceedings of the 1st Workshop on Parallel Problem Solving from Nature
The Fast Evaluation Strategy for Evolvable Hardware

Genetic Programming and Evolvable Machines
An Efficient Multi-Objective Evolutionary Algorithm for Combinational Circuit Design

AHS '06 Proceedings of the first NASA/ESA conference on Adaptive Hardware and Systems
Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm

Genetic Programming and Evolvable Machines
Evolving multiplier circuits by training set and training vector partitioning

ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Evolving hardware by dynamically reconfiguring xilinx FPGAs

ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Promises and challenges of evolvable hardware

IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
A novel genetic algorithm based on immunity

IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans

Fault-tolerance simulation of brushless motor control circuits

EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II

Quantified Score

Hi-index	0.00

Visualization

Abstract

An issue that arises in evolvable hardware is how to verify the correctness of the evolved circuit, especially in online evolution. The traditional exhaustive evaluation approach has made evolvable hardware unpractical to real-world applications. In this paper an incremental evaluation approach for online evolution is proposed, in which the immune genetic algorithm is used as the search engine. This evolution approach is performed in an incremental way: some small seed-circuits have been evolved firstly; then these small seed-circuits are employed to evolve larger module-circuits; and the module-circuits are utilized to build still larger circuits further. The circuits of 8-bit adder, 8-bit multiplier and 110-sequence detector have been evolved successfully. The evolution speed of the incremental evaluation approach appears to be more effective compared with that of the exhaustive evaluation method; furthermore, the incremental evaluation approach can be used both in the combinational logic circuits as well as the sequential logic circuits.