Reducing the number of transistors in digital circuits using gate-level evolutionary design
Proceedings of the 9th annual conference on Genetic and evolutionary computation
Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
Genetic Programming and Evolvable Machines
Research on the online evaluation approach for the digital evolvable hardware
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Fault-tolerance simulation of brushless motor control circuits
EvoApplications'11 Proceedings of the 2011 international conference on Applications of evolutionary computation - Volume Part II
Evolvable hardware design based on a novel simulated annealing in an embedded system
Concurrency and Computation: Practice & Experience
Multi-objective optimization of QCA circuits with multiple outputs using genetic programming
Genetic Programming and Evolvable Machines
Parallel algorithm for evolvable-based boolean synthesis on GPUs
Analog Integrated Circuits and Signal Processing
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Evolutionary design of circuits (EDC), an important branch of evolvable hardware which emphasizes circuit design, is a promising way to realize automated design of electronic circuits. In order to improve evolutionary design of logic circuits in efficiency, scalability and capability of optimization, a genetic algorithm based novel approach was developed. It employs a gate-level encoding scheme that allows flexible changes of functions and interconnections of logic cells comprised, and it adopts a multi-objective evaluation mechanism of fitness with weight-vector adaptation and circuit simulation. Besides, it features an adaptation strategy that enables crossover probability and mutation probability to vary with individuals' diversity and genetic-search process. It was validated by the experiments on arithmetic circuits especially digital multipliers, from which a few functionally correct circuits with novel structures, less gate count and higher operating speed were obtained. Some of the evolved circuits are the most efficient or largest ones (in terms of gate count or problem scale) as far as we know. Moreover, some novel and general principles have been discerned from the EDC results, which are easy to verify but difficult to dig out by human experts with existing knowledge. These results argue that the approach is promising and worthy of further research.