Parallel Random Number Generation for VLSI Systems Using Cellular Automata
IEEE Transactions on Computers
Evolving hardware with genetic learning: a first step towards building a Darwin machine
Proceedings of the second international conference on From animals to animats 2 : simulation of adaptive behavior: simulation of adaptive behavior
Massively parallel artificial intelligence
An evolvable hardware chip and its application as a multi-function prosthetic hand controller
AAAI '99/IAAI '99 Proceedings of the sixteenth national conference on Artificial intelligence and the eleventh Innovative applications of artificial intelligence conference innovative applications of artificial intelligence
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI
ICES '98 Proceedings of the Second International Conference on Evolvable Systems: From Biology to Hardware
An Integrated On-Line Learning System for Evolving Programmable Logic Array Controllers
PPSN VI Proceedings of the 6th International Conference on Parallel Problem Solving from Nature
On-line evolvable fuzzy system for ATM cell-scheduling
Journal of Systems Architecture: the EUROMICRO Journal
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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Evolvable hardware (EHW) is hardware that can change its own circuit structure by genetic learning to achieve maximum adaptation to the environment. In conventional EHW, the learning is executed by software on a computer. However, there are problems associated with this method, of slow learning speeds and large systems, which are serious obstacles to utilizing EHW in various kinds of practical applications. To overcome these problems, we have developed a gate-level evolvable hardware chip, by integrating both GA hardware and reconfigurable hardware within a single LSI chip. The chip consists of genetic algorithm (GA) hardware, reconfigurable hardware logic, and the control logic. With this chip, we have successfully executed GA learning and hardware reconfiguration. In this paper, we describe the architecture, functions, and a performance evaluation of the chip. We show that its learning speed is considerably faster than with software.