Genetic algorithms for VLSI design, layout & test automation
Genetic algorithms for VLSI design, layout & test automation
Evolutionary algorithms for VLSI CAD
Evolutionary algorithms for VLSI CAD
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Principles in the Evolutionary Design of Digital Circuits—Part I
Genetic Programming and Evolvable Machines
EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
ACM SIGARCH Computer Architecture News
A massively parallel architecture for distributed genetic algorithms
Parallel Computing - Special issue: Parallel and nature-inspired computational paradigms and applications
Proceedings of the 9th annual conference companion on Genetic and evolutionary computation
Intel threading building blocks
Intel threading building blocks
Customizable FPGA IP core implementation of a general-purpose genetic algorithm engine
IEEE Transactions on Evolutionary Computation
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
Promises and challenges of evolvable hardware
IEEE Transactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews
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Multicore processors are becoming common whereas current genetic algorithm-based implementation techniques for synthesizing Field Programmable Gate Array (FPGA) circuits do not fully exploit this hardware trend. Genetic Algorithm (GA) based techniques are known to optimize multiple objectives, and automate the process of digital circuit design. In this paper, parallel GA algorithms are proposed for the synthesis of digital circuits for LUT-based FPGA architectures. Parallel modes of the GA such as Master-Slave and the Island model are compared to see which scheme results in better speedup and quicker convergence for effective utilization of current multicore hardware. Speedup of about five over the sequential single-threaded implementation is achieved with both the schemes on a six-core machine. Convergence is also found in fewer number of generations. The methods described here-in can be employed in Evolvable Hardware Systems as well as FPGA CAD tools.