Soft Errors in Advanced Computer Systems
IEEE Design & Test
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Evolving hardware by dynamically reconfiguring xilinx FPGAs
ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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Field Programmable Gate Arrays (FPGAs), are being increasingly used in custom systems requiring fast time-to-market delivery due to their flexibility; being reprogrammable in the field is a real value for long unattended operation and whenever on-site maintenance is costly as is the case in many remote data acquisition stations. The most powerful FPGAs are based in SRAM technology which is particularly prone to transient faults. Fault-tolerance is therefore mandatory and this can be done by simply reprogramming the FPGA, thus repairing the corrupted configuration. Recent advances in FPGA technology allow the configuration of just a portion of the FPGA, which lowers significantly the time overhead, while the remaining parts are running. This truly dynamic partial FPGA reconfiguration can be used to provide fault-tolerance for hard real-time applications, guaranteeing high reliability in long missions. This short paper addresses the technological aspects of partial dynamic reconfigurable FPGAs, presents some of most important threats to dependability of these devices, and identifies some research areas to investigate in order to increase dependability.