EH '99 Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware
Self-Assembling Circuits with Autonomous Fault Handling
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
Bridging The Genotype-Phenotype Mapping For Digital Fpgas
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
An In-System Routing Strategy For Evolvable Hardware Programmable Platforms
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Dynamic reconfiguration in FPGA-based SoC designs (abstract only)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
POEtic tissue: an integrated architecture for bio-inspired hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Virtual reconfigurable circuits for real-world applications of evolvable hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
A reconfigurable architecture for emulating large-scale bio-inspired systems
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
Design of a cell in embryonic systems with improved efficiency and fault-tolerance
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
IWANN'11 Proceedings of the 11th international conference on Artificial neural networks conference on Advances in computational intelligence - Volume Part II
Genetic Algorithm for Boolean minimization in an FPGA cluster
The Journal of Supercomputing
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This paper will present the final hardware realization of a new family of programmable devices that has specifically being conceived in order to address the prototyping of bio-inspired principles. The devices are organized around a custom 32-bit RISC microprocessor and a custom FPGA. The internal architecture devised for the devices is scalable, so that it is possible to construct a physical hardware platform whose size matches the requirements of the application to be handled. To facilitate the development of applications for this hardware platform a complete set of design tools has been developed.