Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities

Authors:
Javier Soto;Juan Manuel Moreno;Joan Cabestany
Affiliations:
Department of Electronic Engineering, Technical University of Catalunya (UPC), Barcelona, Spain;Department of Electronic Engineering, Technical University of Catalunya (UPC), Barcelona, Spain;Department of Electronic Engineering, Technical University of Catalunya (UPC), Barcelona, Spain
Venue:
IWANN'11 Proceedings of the 11th international conference on Artificial neural networks conference on Advances in computational intelligence - Volume Part II
Year:
2011

Citing 5
Cited 0

Self-Assembling Circuits with Autonomous Fault Handling

EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
An In-System Routing Strategy For Evolvable Hardware Programmable Platforms

EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture

RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Formalizing SANE virtual processor in thread algebra

ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
POEtic: a prototyping platform for bio-inspired hardware

ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way selfadaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration.