Self-Assembling Circuits with Autonomous Fault Handling
EH '02 Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware (EH'02)
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EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
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ICFEM'07 Proceedings of the formal engineering methods 9th international conference on Formal methods and software engineering
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ICES'05 Proceedings of the 6th international conference on Evolvable Systems: from Biology to Hardware
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This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. Additionally, it is described as an example application and a software tool that has been implemented to facilitate the development of applications to test the system.