The lifting scheme: a construction of second generation wavelets
SIAM Journal on Mathematical Analysis
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JPEG 2000: Image Compression Fundamentals, Standards and Practice
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Evolution strategies –A comprehensive introduction
Natural Computing: an international journal
Introduction to Evolutionary Computing
Introduction to Evolutionary Computing
Effective image compression using evolved wavelets
GECCO '05 Proceedings of the 7th annual conference on Genetic and evolutionary computation
An Evaluation of the Suitability of FPGAs for Embedded Vision Systems
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Workshops - Volume 03
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Computing in Science and Engineering
An evolvable hardware system in Xilinx Virtex II Pro FPGA
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SSIP'06 Proceedings of the 6th WSEAS International Conference on Signal, Speech and Image Processing
A differential evolution algorithm for optimizing signal compression and reconstruction transforms
Proceedings of the 10th annual conference companion on Genetic and evolutionary computation
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SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference: Late Breaking Papers
Adaptive lifting schemes with perfect reconstruction
IEEE Transactions on Signal Processing
Optimization and implementation of the integer wavelet transform for image coding
IEEE Transactions on Image Processing
Wavelet filter evaluation for image compression
IEEE Transactions on Image Processing
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling
Microprocessors & Microsystems
Genetic wavelet packets for speech recognition
Expert Systems with Applications: An International Journal
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A bioinspired, evolutionary algorithm for optimizing wavelet transforms oriented to improve image compression in embedded systems is proposed, modelled, and validated here. A simplified version of an Evolution Strategy, using fixed point arithmetic and a hardware-friendly mutation operator, has been chosen as the search algorithm. Several cutdowns on the computing requirements have been done to the original algorithm, adapting it for an FPGA implementation. The work presented in this paper describes the algorithm as well as the test strategy developed to validate it, showing several results in the effort to find a suitable set of parameters that assure the success in the evolutionary search. The results show how high-quality transforms are evolved from scratch with limited precision arithmetic and a simplified algorithm. Since the intended deployment platformis an FPGA, HW/SW partitioning issues are also considered as well as code profiling accomplished to validate the proposal, showing some preliminary results of the proposed hardware architecture.