Real-time high-definition stereo matching on FPGA
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Hardware design considerations for edge-accelerated stereo correspondence algorithms
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm
Computer Vision and Image Understanding
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Information permeability for stereo matching
Image Communication
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High-performance real-time stereo vision system is crucial to various stereo vision applications, such as robotics, autonomous vehicles, multiview video coding, freeview TV, and 3-D video conferencing. In this paper, we proposed a high-performance hardware-friendly disparity estimation algorithm called mini-census adaptive support weight (MCADSW) and also proposed its corresponding real-time very large scale integration (VLSI) architecture. To make the proposed MCADSW algorithm hardware-friendly, we proposed simplification techniques such as using mini-census, removing proximity weight, using YUV color representation, using Manhattan color distance, and using scaled-and-truncate weight approximation. After applied these simplifications, the MCADSW algorithm was not only hardware-friendly, but was also 1.63 times faster. In the corresponding real-time VLSI architecture, we proposed partial column reuse and access reduction with expanded window to significantly reduce the bandwidth requirement. The proposed architecture was implemented using United Microelectronics Corporation (UMC) 90 nm complementary metal-oxide-semiconductor technology and can achieve a disparity estimation frame rate of 42 frames/s for common intermediate format size images when clocked at 95 MHz. The synthesized gate-count and memory size is 563 k and 21.3 kB, respectively.