Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Silicon germanium hbt bicmos field programmable gate arrays for fast reconfigurable computing
Silicon germanium hbt bicmos field programmable gate arrays for fast reconfigurable computing
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.