CORDIC Architectures with Parallel Compensation of the Scale Factor

Authors:
J. Villalba;J. A. Hidalgo;E. L. Zapata;E. Antelo;J. D. Bruguera
Affiliations:
-;-;-;-;-
Venue:
ASAP '95 Proceedings of the IEEE International Conference on Application Specific Array Processors
Year:
1995

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Abstract

The compensation of scale factor imposes significant computation overhead on the CORDIC algorithm. In this paper we will propose two algorithms and architectures in order to perform the compensation of the scale factor in parallel with the computation of the CORDIC iterations. This way it is not necessary to carry out the final multiplication or add scaling iterations in order to achieve the compensation. With the architectures we propose the dependence on n of the compensation of the scale factor disappears, and this considerably reduces the latency of the system. The architectures developed are optimized solutions for the different operating modes of the CORDIC both in conventional and in redundant arithmetic.