Evaluation of CORDIC Algorithms for FPGA Design
Journal of VLSI Signal Processing Systems
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A unified algorithm for elementary functions
AFIPS '71 (Spring) Proceedings of the May 18-20, 1971, spring joint computer conference
IEEE Communications Magazine
Configurable logic for digital communications: some signal processing perspectives
IEEE Communications Magazine
A quantitative analysis of the speedup factors of FPGAs over processors
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems
Journal of Signal Processing Systems
50 years of CORDIC: algorithms, architectures, and applications
IEEE Transactions on Circuits and Systems Part I: Regular Papers
| Hi-index | 0.00 |
This paper deals with the optimized implementation of high performance coherent demodulators in FPGAs for the DVB standard. This work provides design guidelines in order to optimize fixed-point demodulation loops in terms of symbol rate. Several schemes are evaluated such as ROM partitioning techniques and the CORDIC algorithm. We go through the whole design process from simulation to timing analysis for a particular case study. For each architecture we propose the most efficient design for Virtex FPGAs in terms of area and throughput. Finally we will compare them in order to establish the most suitable de-rotator scheme for each transmission bandwidth, and for transmission rates up to 25.8 Mbauds.