A technology independent MOS multiplier generator

Authors:
Kung-chao Chu;Ramautar Sharma
Affiliations:
Bell Laboratories, Murray Hill, New Jersey;Bell Laboratories, Murray Hill, New Jersey
Venue:
DAC '84 Proceedings of the 21st Design Automation Conference
Year:
1984

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Abstract

A layout generator for technology independent implementation of the MOS multiplier is described. The modified Booth's algorithm with a structured floor plan has been used. The layout has been optimized and described as a program in a high level layout language. The fabrication process related information is maintained in a separate technology database that is coupled with the layout program at the time of execution to generate the mask data. The user can choose from a variety of architectures for speed, area, and power trade-off's. The user can also specify geometric and electrical constraints tailored to his system specification.