Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels

Authors:
Khurram Muhammad;Robert B. Staszewski;Poras T. Balsara
Affiliations:
Texas Instruments Inc., Dallas, TX;Texas Instruments Inc., Dallas, TX;Univ. of Texas at Dallas, Richardson, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Year:
2001

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Abstract

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed and latency remain as the main performance criteria for the target application. The proposed parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed, and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18-/spl mu/m L-effective CMOS technology and operates at 550 MSamples/s. Trading off filter latency to improve speed is also discussed.