The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell
Microelectronics Journal
A 32-bit carry lookahead adder using dual-path all-n logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposed two full adder circuits such as mixed Shannon and Shannon theorem based adder circuits. The mixed adder circuit developed by using MCIT for the sum operation and Shannon technique for carry and other one designed completely by using Shannon theorem. The ALU circuit consists of AND, OR, multiplexer and adder circuits that are designed by using proposed Shannon theorem. The 32-bit ALU circuits are analyses by BSIM 4 parameter analyzer. The power dissipation of total circuit, propagation delay and area are analyzed for 32 bit ALU. The binvert Shannon adder based ALU circuit gives better performance in terms of power dissipation, propagation delay, and throughput than bit-sliceALU circuit.