ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
A low power high-speed 8-bit pipelining CLA design using dual-threshold voltage domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient EPI and energy consumption of 32 bit ALU using Shannon theorem based adder approach
WSEAS Transactions on Circuits and Systems
A new construction adder based on Chinese abacus algorithm
Computers and Electrical Engineering
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We have developed dual path all-N logic (DPANL)and applied it to 32-bit adder design for higher performance. The speed is significantly enhanced due to reduced capacitance at each evaluation node of dynamic circuits. The power saving is achieved due to reduced adder cell size and minimal race problem. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35-µm 1P4M CMOS technology and is 32.4% faster than the adder using all-N transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35-µm CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.