Multi-voltage low power convolvers using the polynomial residue number system
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Modified Booth Modulo 2^n-1 Multipliers
IEEE Transactions on Computers
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
High-radix residue arithmetic bases for low-power DSP systems
DSP'09 Proceedings of the 16th international conference on Digital Signal Processing
Residue arithmetic for designing low-power multiply-add units
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Residue arithmetic for variation-tolerant design of multiply-add units
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper proposes an efficient algorithm for multiplication modulo (2/sup N/-1). To achieve high speed, the Wallace tree is adopted for the multiplier. The Wallace tree multiplier exhibits a more regular structure than binary Wallace tree multipliers, and comparisons with published designs demonstrates advantages of our multiplier architecture in both speed and hardware.