Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 42nd annual Design Automation Conference
A statistical approach for full-chip gate-oxide reliability analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
IBM Journal of Research and Development
Post-fabrication measurement-driven oxide breakdown reliability prediction and management
Proceedings of the 2009 International Conference on Computer-Aided Design
Robust Extraction of Spatial Correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
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Gate oxide breakdown is a major cause of reliability failures in future nanometer-scale CMOS designs. This paper develops an analysis technique that can predict the probability of a functional failure in a large digital circuit due to this phenomenon. Novel features of the method include its ability to account for the inherent resilience in a circuit to a breakdown event, while simultaneously considering the impact of process variations. Based on standard process variation models, at a specified time instant, this procedure determines the circuit failure probability as a lognormal distribution. Experimental results demonstrate this approach is accurate compared with Monte Carlo simulation, and gives 4.7--5.9x better lifetime prediction over existing methods that are based on pessimistic area-scaling models.