Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An array-based test circuit for fully automated gate dielectric breakdown characterization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit reliability: from physics to architectures
Proceedings of the International Conference on Computer-Aided Design
Scalable methods for analyzing the circuit failure probability due to gate oxide breakdown
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The limitations of reliability of silicon dioxide dielectric for future CMOS scaling are investigated. Several critical aspects are examined, and new experimental results are used to form an empirical approach to a theoretical framework upon which the data is interpreted. Experimental data over a wide range of oxide thickness (TOX), voltage, and temperature were gathered using structures with a wide range of gate-oxide areas, and over very long stress times. This work resolves seemingly contradictory observations regarding the temperature dependence of oxide breakdown. On the basis of these results, a unified, global picture of oxide breakdown is constructed, and the resulting model is applied to project reliability limits for the wear-out of silicon dioxide. It is concluded that silicon-dioxide-based materials can provide a reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable to the 50-nm-technology node using silicon-dioxide-based gate insulators.