Efficient library characterization for high-level power estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multimode power modeling and maximum-likelihood estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Statistical full-chip total power estimation considering spatially correlated process variations
Integration, the VLSI Journal
| Hi-index | 0.00 |
In this paper, we propose two efficient statistical sampling techniques for estimating the total power consumption of large hierarchical circuits. We first show that, due to the characteristic of the sampling efficiency in Monte Carlo simulation, granularity of samples is an important issue in achieving high overall efficiency. The proposed techniques perform sampling both temporally (across different clock cycles) and spatially (across different modules) so that a smaller sample granularity can be achieved while maintaining the normality of samples. The first proposed technique, which is referred to as the module-based approach, samples each module independently when forming a power sample. The second technique, which is referred to as the cluster-based approach, lumps the modules of a hierarchical circuit into a number of clusters on which sampling is then performed. Both techniques adapt stratification to further improve the efficiency. Experimental results show that these techniques provide a reduction of 23/spl times/ in simulation run time compared to existing Monte-Carlo simulation techniques.