Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Digital Logic Design Principles
Digital Logic Design Principles
Low-Power, High-Speed CMOS VLSI Design
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Power Dissipation of CMOS circuits can be reduced by 50% - 80% by lowering switching activity. In practice, power reduction by an order of 10% - 50% can be obtained by appropriate design efforts [1]. In this paper, an approach is presented for minimizing the power consumption of static digital circuits, based on a function realization method, which employs hybrid gate logic. This approach aims at minimizing the worst case circuit switching activity, transition activity factor, while simultaneously fostering uniformity in the individual gate switching activity, besides reducing it. The universal logic gates with varying inputs and the inverter used in the non-regenerative circuits, were designed using MOS transistors based on 3.3V, 0.5 µm CMOS technology. A significant number of digital circuits were designed and an average reduction in power consumption of the order of 20% - 25% was achieved by way of the proposed synthesis technique, in comparison with the conventional one. The accuracy of the approach is verified by comparing the values calculated by an extension of the method outlined in [2], with that obtained through SPICE simulation studies and they are found to be in close agreement, thus highlighting the usefulness of the proposed strategy, especially for multilevel digital architectures.