Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Introduction to algorithms
Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Shift Register Sequences
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
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A test pattern generator (TPG) for built-in self-test(BIST), which can reduce heat dissipation during testapplication, is proposed. The proposed TPG, calleddual-speed LFSR (DS-LFSR), consists of two linearfeedback shift registers (LFSR's), a slow LFSR anda normal-speed LFSR. The slow LFSR is driven by aslow clock whose speed is l/dth that of the normalclock which drives the normal-speed LFSR. The useof DS-LFSR lowers the transition density at the circuitinputs driven by the slow LFSR, leading to a reductionin heat dissipation during test application. Aprocedure is presented to design a DS-LFSR so as toachieve high fault coverage by ensuring that patternsgenerated by it are unique and uniformly distributed.A new gain function, and a method to compute itsvalue for each circuit input, is proposed to select inputsto be driven by the slow LFSR. Also, a procedureto increase the number of inputs driven by theslow LFSR by combining compatible inputs is presentedto further decrease the heat dissipation. Finally,DS-LFSR's are designed for the ISCAS85 andISCAS89 benchmark circuits and shown to provide13% to 70% reduction in the numbers of transitionswith no loss of fault coverage and at very slight areaoverheads.