Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network states. This analysis supports the same class of networks as the switch-level simulator MOSSIM II and provides the same functionality, including the handling of bidirectional effects and indeterminate (X) logic values. In the worst case, the analysis of an n-node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, pass-transistor networks give formulas with O(n) total operations. The analysis can serve as the basis of efficient programs for a variety of logic design tasks, including logic simulation (on both conventional and special-purpose computers), fault simulation, test generation, and symbolic verification.