Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
SBCCI '98 Proceedings of the 11th Brazilian Symposium on Integrated circuit design
A New On-Line Robust Approach to Design Noise-Immune Speech Recognition Systems
Journal of Electronic Testing: Theory and Applications
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Journal of Electronic Testing: Theory and Applications
Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Journal of Electronic Testing: Theory and Applications
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We present hereafter a new approach to estimate the reliability of complex circuits used in harmful environments like radiation. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities (particle accelerators). In our case, we estimate the expected tolerance of the complex circuit with respect to SEU during the VHDL specification step. By doing so, the early-estimated reliability level is used to balance the design process into a trade-off between maximum area overhead due to the insertion of redundancy and the minimum reliability required for a given application. This approach is being automated through the development of a CAD tool.