Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Fundamentals of speech recognition
Fundamentals of speech recognition
Digital signal processing (3rd ed.): principles, algorithms, and applications
Digital signal processing (3rd ed.): principles, algorithms, and applications
Fault-tolerant computer system design
Fault-tolerant computer system design
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
Discrete Time Processing of Speech Signals
Discrete Time Processing of Speech Signals
Transient-fault tolerant VHDL descriptions: a case-study for area overhead analysis
ATS '00 Proceedings of the 9th Asian Test Symposium
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Journal of Electronic Testing: Theory and Applications
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Hereafter, we present a new approach dealing to cope with the harmful effects of noise on speech recognition systems (SRS). This approach is oriented to hardware redundancy and it is essentially a modification of the classic Recovery Blocks scheme. When compared to conventional approaches using Fast Fourier Transform (FFT) and Hamming Code, the primary benefit of such a technique is to improve system performance when operating in real (i.e., noisy) environments. The second advantage is related to the considerably low complexity and reduced area overhead required for implementation. We implemented three full versions of the proposed algorithm: one running of a PC microcomputer, and a second one slightly modified to run on a TMS-320C67 Texas DSP microprocessor module. Both of them were described in the C language. Finally, a last implementation was prototyped on a HW-SW development environment based on the same Texas microprocessor and on the FLEX10K20 FPGA Altera Component.