CHOP: A constraint-driven system-level partitioner
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This paper describes the tight integration of design space exploration with spatial and temporal partitioning algorithms in the SPARCS design automation system for RCs. In particular, this paper describes a novel technique to perform efficient design space exploration of parallel-process behaviors using the knowledge of spatial partitioning. The exploration technique satisfies the design latency constraints imposed by temporal partitioning and the device area constraints of the RC. Results clearly demonstrate the effectiveness of the partitioning knowledgeable exploration technique in guiding spatial partitioning to quickly converge to a constraint satisfying solution. Results of design automation through SPARCS and testing designs on a commercial RC board are also presented.