Automatic module allocation in high level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Cosimulation of real-time control systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Debugging of behavioral VHDL specifications by source level emulation
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
A backplane approach for cosimulation in high-level system specification environments
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Design-for-debugging of application specific designs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
RTL emulation: the next leap in system verification
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A prototyping environment for hardware/software codesign in the COBRA project
CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
Visions for application development on hybrid computing systems
Parallel Computing
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We present an approach for accelerating the validation speed of behavioral system descriptions through hardware emulation. The method allows source-level debuggingof running hardware specified in behavioral VH DL in a way similar to sorce-leve debugging in software programing languages. We discuss breakpoints in source-level emulation and how the circuit generated by high-level synthesis has to be modified to work with breakpoints. Breakpoint encoding and detection are shown in detail. Our approach allows breakpoint detection by hardware with seriously slowing the circuit or dramitically increasing its size.