REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Adapting a debugger for optimised programs
ACM SIGPLAN Notices
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Symbolic Debugging of Optimized Code
ACM Transactions on Programming Languages and Systems (TOPLAS)
Fast Prototyping of Datapath-Intensive Architectures
IEEE Design & Test
An interactive high-level debugger for control-flow optimized programs
SIGSOFT '83 Proceedings of the symposium on High-level debugging
A quantitative approach to functional debugging
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Breakpoints and breakpoint detection in source-level emulation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 38th annual Design Automation Conference
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
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Abstract: We address the problem of considering debugging requirements during high level synthesis by providing low-cost hardware support and scheduling and assignment methods for ensuring controllability and observability of the user specified variables. Two key conceptually new design ideas that enable efficient debugging are developed: pipelining of debugging variables for improving their scheduling and assignment freedom and use of I/O buffers for improving resource utilization of I/O pins. The provably optimal bounds for the maximum cardinality of the set of controllable and observable variables for a given design specification are derived. A polynomial time complexity synthesis algorithm for achieving the bounds is developed. The minimization of hardware overhead gives rise to a combinatorial optimization problem which is solved using a non-greedy heuristic algorithm. The effectiveness of the proposed Design-for-Debugging approach is demonstrated on several examples.