The annealing algorithm
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
A memory selection algorithm for high-performance pipelines
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Optimal register assignment to loops for embedded code generation
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Area and performance optimizations in path-based scheduling
EURO-DAC '91 Proceedings of the conference on European design automation
Increasing hardware efficiency with multifunction loop accelerators
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A functional unit and register binding algorithm for interconnect reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In previous research interconnection was optimised when the module allocation for the operations and the register allocation for the variables already had been done. However, both the amount of multiplexing and interconnect are crucial factors to both the delay and the area of a circuit. In this paper it is shown that when variables are grouped into register files and operations are assigned to modules to minimise the interconnections, significant savings (20%) can be obtained in the number of local interconnections and the amount of global interconnect on the expense of only slightly more register area. This can be enhanced by splitting read and write phases of registers and even more by introducing serial(re-)write operations for the same value. The variable grouping is based on edge colouring algorithms that provide a sharp upper bound on the number of colours needed.