VLSI array processors
Loop skewing: the wavefront method revisited
International Journal of Parallel Programming
Detecting cycles in dynamic graphs in polynomial time
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Strongly polynomial-time and NC algorithms for detecting cycles in dynamic graphs
STOC '89 Proceedings of the twenty-first annual ACM symposium on Theory of computing
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
An effective methodology for functional pipelining
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
A Loop Transformation Theory and an Algorithm to Maximize Parallelism
IEEE Transactions on Parallel and Distributed Systems
Constructive Methods for Scheduling Uniform Loop Nests
IEEE Transactions on Parallel and Distributed Systems
Loop Quantization: an Analysis and Algorithm
Loop Quantization: an Analysis and Algorithm
Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 02
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns
Proceedings of the 6th international workshop on Hardware/software codesign
Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation
Journal of VLSI Signal Processing Systems
Combining extended retiming and unfolding for rate-optimal graph transformation
Journal of VLSI Signal Processing Systems
Execution Time Optimization Using Delayed Multidimensional Retiming
DS-RT '12 Proceedings of the 2012 IEEE/ACM 16th International Symposium on Distributed Simulation and Real Time Applications
| Hi-index | 0.00 |
The design of multi-dimensional systems using hardware/software codesign allows a significant improvement in the development cycle. This paper presents a technique that enables a design to have arbitrarily high throughput by using multi-dimensional retiming techniques while adjusting the composition of hardware and multiple software elements in order to satisfy the area requirements. A multi-dimensional graph representing the problem is transformed and scheduled such that all nodes are executed in a fully parallel way. The techniques presented are applicable to any problem which can be represented as a multi-dimensional data flow graph. Results are shown which illustrate the efficiency of the system as well as the savings achieved.