An application of exploratory data analysis techniques to floorplan design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Flexible controlpath microarchitecture synthesis based on artificial intelligence
EURO-DAC '92 Proceedings of the conference on European design automation
State assignment for hardwired VLSI control units
ACM Computing Surveys (CSUR)
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
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We present a new form of partitioning of PLA-based FSMs that combines the advantages of traditional vertical PLA partitioning (i.e. via inputs and/or outputs) and counter embedding which consists of replacing the FSM state memories by a counter. Like the former, horizontal partitioning allows the reduction of the number of input and/or output columns in the PLAs resulting from the partition. Furthermore, the technique also reduces the total number of product terms, as in counter embedding techniques. This reduction is due to a decomposition of state transitions into two classes that are realized by two sets of logic. In this case however, a second PLA-based FSM is used in place of the counter. This results in area reductions of 30% to 60% (with respect to regular two-level logic minimization) for the benchmark examples presented.