Fast heuristic algorithms for finite state machine minimization

Authors:
L. N. Kannan;D. Sarma
Affiliations:
Cadence Design Systems, Santa Clara, CA;Rutgers University, Camden, NJ
Venue:
EURO-DAC '91 Proceedings of the conference on European design automation
Year:
1991

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Abstract

In this paper, a technique for the minimization of completely and incompletely specified sequential machines is described. By employing fast heuristic algorithms, it has been shown that it is possible to effectively reduce large (121 states) finite state machines in reasonable computing time when compared to other methods. It has been shown that it is possible to achieve area/literal reductions in the range of 30--100% over unreduced machines using this technique.