Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
Test Scheduling and Control for VLSI Built-in Self-Test
IEEE Transactions on Computers
The Architecture of Symbolic Computers
The Architecture of Symbolic Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
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The authors provide tools for exploring the inherent parallelism introduced by design for testability (DFT) and built-in self-test (BIST) techniques in order to reduce test length. Since the potential for parallel test execution is most apparent at the organization level and DFT and BIST hardware is also often added at that level, the organization level is used as a foundation for the work. A broader modeling foundation that encompasses both dimensions, space and time, of test parallelism is introduced. A set of simple schedulability criteria for concurrent issuing of tests is developed. Effective suboptimum heuristic-based algorithms for scheduling tests on general-purpose high-performance VLSI system implementation are presented. The scheduling algorithms have been implemented and performance results are presented.