Test scheduling for high performance VLSI system implementations

Authors:
John Sayah;Charles R. Kime
Affiliations:
Department of Electrical and Computer Engineering, University of Wisconsin, Madison, Wisconsin;Department of Electrical and Computer Engineering, University of Wisconsin, Madison, Wisconsin
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

Citing 4
Cited 0

Test Schedules for VLSI Circuits Having Built-In Test Hardware

IEEE Transactions on Computers - The MIT Press scientific computation series
Test Scheduling and Control for VLSI Built-in Self-Test

IEEE Transactions on Computers
Computers and Intractability: A Guide to the Theory of NP-Completeness

Computers and Intractability: A Guide to the Theory of NP-Completeness
Design And Test of the 80386

IEEE Design & Test

Quantified Score

Hi-index	0.00

Visualization

Abstract

Advances in VLSI technologies permit the implementation of complex computers on a single chip. Testing high performance VLSI systems containing pipelines and multifunctional units is a formidable task due to the complexity of the implementations. One of the most important problems facing test designers is the time required to perform satisfactory testing. Exploiting the potential testing parallelism is essential for reducing the total test time. Previous work in test scheduling dealt with single aspects of test parallelism. In this paper, a broader modeling foundation that encompasses both dimensions, space and time, of the test parallelism space is introduced. A powerful suboptimum heuristic for scheduling tests on general purpose high performance VLSI system implementations is presented. The scheduling algorithm has been implemented and performance results are presented.