A memory grouping method for sharing memory BIST logic

Authors:
Masahide Miyazaki;Tomokazu Yoneda;Hideo Fujiwara
Affiliations:
Nara Institute of Science and Technology (NAIST), Takayama, Ikoma, Japan;Nara Institute of Science and Technology (NAIST), Takayama, Ikoma, Japan;Nara Institute of Science and Technology (NAIST), Takayama, Ikoma, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results showed that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also showed that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.