Particle swarm optimization based BIST design for memory cores in mesh based network-on-chip

Authors:
Bibhas Ghoshal;Subhadip Kundu;Indranil Sengupta;Santanu Chattopadhyay
Affiliations:
Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, India;Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, India;Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, India;Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, Kharagpur, India
Venue:
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Year:
2012

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Abstract

Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solution for testing embedded memory cores in Systems-On-Chip. The reuse of the available on-chip network to act as Test Access Mechnism brings down the area overhead as well as reduces test power. However, reducing the time to test still remains a problem due to latency in transporting the test instruction from BIST circuit to the memory cores. We have proposed a NoC based test architecture where a number of BIST controllers are shared by memory cores. A Particle Swarm Optimization (PSO) based technique is used (i) to place the BIST controllers at fixed locations and (ii) to form clusters of memories sharing the BIST controllers. This reduces the test instruction transport latency which in turn reduces the total test time of memory cores. Experimental results on different sizes of mesh based NoC confirm the effectiveness of our PSO based approach over heuristic techniques reported in literature as well as used in the industry.