A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing Embedded Cores Using Partial Isolation Rings
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.1 Test methodology for embedded cores which protects intellectual property
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fault isolation for nonisolated blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We consider issues related to the testing of a legacy core ded in user-defined logic. We assume that the only information available about the core is its test set. We provide procedures for testing the core and its surrounding logic without adding DFT logic. The procedures maximize the information extracted from the test set given for the core, in order to maximize the fault coverage achieved without DFT. We also describe DFT insertion procedures. The core and the surrounding logic are considered simultaneously during DFT insertion to minimize the amount of DFT logic required.