Fast seed computation for reseeding shift register in test pattern compression

Authors:
Nahmsuk Oh;Rohit Kapur;T. W. Williams
Affiliations:
Synopsys Inc., Mountain View, CA;Synopsys Inc., Mountain View, CA;Synopsys Inc., Mountain View, CA
Venue:
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Year:
2002

Citing 4
Cited 0

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers

IEEE Transactions on Computers - Special issue on fault-tolerant computing
Test Data Decompression for Multiple Scan Designs with Boundary Scan

IEEE Transactions on Computers
Two-Dimensional Test Data Decompressor for Multiple Scan Designs

Proceedings of the IEEE International Test Conference on Test and Design Validity
Test vector encoding using partial LFSR reseeding

Proceedings of the IEEE International Test Conference 2001

Quantified Score

Hi-index	0.00

Visualization

Abstract

Solving a system of linear equations has been widely used to compute seeds for LFSR reseeding to compress test patterns. However, as chip size is growing, solving linear equations requires a large number of computations that is proportional to n3. This paper proposes a new scan chain architecture and algorithm so that the order of computation is proportional to the number of scan cells in a chip. The new architecture is a methodology change that does not require complex Design-For-Testability (DFT) as proposed in the previous techniques. Instead of solving linear equations, the proposed new seed computation algorithm topologically determines seeds for test vectors. The compression ratio might be slightly lower than the other approaches, but the proposed approach can handle larger designs in a reasonable amount of time. Computation analysis shows that, for 1 million scan cell design, if we assume it takes 1 msec for the proposed technique to compute seeds, it would take more than 14 minutes for other techniques that solve linear equations.