A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Using a single input to support multiple scan chains
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
A Serial-Scan Test-Vector-Compression Methodology
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test set compaction for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RL-huffman encoding for test compression and power reduction in scan applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Conventional scan-based designs spend a lot of testing time in shifting test patterns and output responses, which greatly increases the testing cost. In this paper, we propose a modified approach for scan-based design in which a test is conducted in every clock cycle. This approach may significantly reduce the test application time when appropriate test vectors are applied. We develop algorithms to generate efficient test input for the test environment, and experimental results show that we can achieve high fault coverage with only about 10%-30% of the clock cycles required in conventional scan-based design.