A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
A design for testability scheme with applications to data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An exact algorithm for selecting partial scan flip-flops
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resynthesis and retiming for optimum partial scan
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testability improvement in high-level synthesis through reconvergence reduction
ASILOMAR '95 Proceedings of the 29th Asilomar Conference on Signals, Systems and Computers (2-Volume Set)
Structural constraints for circular self-test paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Hardware-optimal test register insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast Computation of Data Correlation Using BDDs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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A new partial BIST insertion approach based on eliminating data correlation to improve pseudo-random testability is presented. Data correlation causes the circuit to be in a subset of the states more or less frequently, which leads to low fault coverage in pseudo-random test. One important cause of correlation is reconvergent fanout. Incorporating BIST test flip-flops into reconvergent paths will break correlation, however, breaking all reconvergent fanout is unnecessary since some reconvergent fanout results in negligible correlation. We introduce a metric to determine the degree of correlation caused by a set of reconvergent fanout paths. We use this metric to identify problematic reconvergent fanout which must be broken through partial BIST insertion. We provide an algorithm to break high correlation reconvergent paths. Our algorithm provides high fault coverage while selecting fewer BIST flip-flops than required using loop breaking techniques. Experimental results produced using our algorithm rank on average among the top 11.6% of all possible solutions with the same number of flip-flops.